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revision-K1.1e, ' 99.10.21
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5408B is a family of 4-Mbit static RAMs organized as 524,288-words by 8-bit, fabricated by Mitsubishi's highperformance 0.25m CMOS technology. The M5M5408B is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. M5M5408B is packaged in 32-pin plastic SOP and 32-pin plastic TSOP packages. Two types of TSOPs are available , M5M5408BTP (normal-lead-bend TSOP) and M5M5408BRT (reverse-lead-bend TSOP). These two types TSOPs are suitable for a surface mounting on double-sided printed circuit boards. From the point of operating temperature, the family is divided into three versions; "Standard", "W-version", and "I-version". Those are summarized in the part name table below.
FEATURES
* Single +5V power supply * Small stand-by current: 0.4A(3V,typ.) * No clocks, No refresh * Data retention supply voltage=2.0V to 5.5V * All inputs and outputs are TTL compatible. * Easy memory expansion by S * Common Data I/O * Three-state outputs: OR-tie capability * OE prevents data contention in the I/O bus * Process technology: 0.25m CMOS * Package: M5M5408BFP: 32 pin 525 mil SOP M5M5408BTP/RT: 32 pin 400 mil TSOP(ll)
PART NAME TABLE
Version, Operating temperature Part name (## stands for "FP","TP","RT") M5M5408B## -55L
Power Supply
Access time
Stand-by current Icc(PD), Vcc=3.0V typical * Ratings (max.) 25C --70C 50A 85C ---
max.
55ns
Active current Icc1 (5.0V, typ.)
Standard 0 ~ +70C
M5M5408B## -70L M5M5408B## -55H
5.0V
70ns 55ns
5.0V M5M5408B## -70H M5M5408B## -55LW 5.0V 70ns 55ns
0.4A
15A
---
--70ns 55ns
---
100A
50mA (10MHz) 25mA (1MHz)
W-version -20 ~ +85C
M5M5408B## -70LW M5M5408B## -55HW 5.0V M5M5408B## -70HW M5M5408B## -55LI 5.0V
0.4A 70ns 55ns --70ns 55ns
---
30A
---
100A
I-version -40 ~ +85C
M5M5408B## -70LI M5M5408B## -55HI 5.0V M5M5408B## -70HI
0.4A 70ns
---
30A
* "typical" parameter is sampled, not 100% tested.
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revision-K1.1e, ' 99.10.21
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
PIN CONFIGURATION (TOP VIEW)
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 (0V) GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC (5V) A15 A17 W A13 A8 A9 A11 OE A10 S DQ8 DQ7 DQ6 DQ5 DQ4
Outline
32P2M-A (FP) 32P3Y-H (TP)
(5V) VCC
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A15 A17 W A13 A8 A9 A11 OE A10 S DQ8 DQ7 DQ6 DQ5 DQ4
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND (0V)
Outline
32P3Y-J (RT)
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revision-K1.1e, ' 99.10.21
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The M5M5408BFP,TP,RT is organized as 524,288-words by 8-bit. These devices operate on a single +5.0V power supply, and are directly TTL compatible to both input and output. Its fully static circuit needs no clocks and no refresh, and makes it useful. A write operation is executed during the S low and W low overlap time. The address(A0~A18) must be set up before the write cycle A read operation is executed by setting W at a high level and OE at a low level while S are in an active state(S=L). When setting S at a high level, the chips are in a nonselectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips. Setting the OE at a high level,the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. The power supply current is reduced as low as 0.4A(25C, typical), and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.
FUNCTION TABLE
S H L L L W X L H H OE X X L H Mode Non selection Write Read Read DQ High-impedance Data input (D) Data output (Q) High-impedance Icc Standby Active Active Active
Pin A0 ~ A18 S W OE Vcc GND
Function Address input Chip select input Write control input Output inable input Power supply Ground supply
DQ1 ~ DQ8 Data input / output
BLOCK DIAGRAM
M5M5408B FP/TP/RT M5M5408B FP/TP/RT
13 14
A4 A5 A6 A7 A12 A14 A16 A17 A18 A15 A10 A11 A9 A8 A13
8 7 6 5 4 3 2 30 1 31
MEMORY ARRAY 524288 WORDS x 8 BITS
15 17 18 19 20 21
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
23 25 26 27 28 29 22 24
CLOCK GENERATOR
W S OE VCC
(5V)
A0 A1 A2 A3
12 11 10 9
32
16
GND
(0V)
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revision-K1.1e, ' 99.10.21
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND With respect to GND With respect to GND Ta=25C Standard (-L, -H) (-LW, -HW) (-LI, -HI) W-version I-version Ratings Units
Vcc VI VO Pd Ta Tstg
-0.3* ~ +7 -0.3* ~ Vcc + 0.3 0 ~ Vcc 700 0 ~ +70 -20 ~ +85 -40 ~ +85 -65 ~150
V mW C C
* -3.0V in case of AC (Pulse width 30ns)
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter High-level input voltage Low-level input voltage High-level output voltage 1 IOH= -1mA High-level output voltage 2 IOH= -0.1mA Low-level output voltage Input leakage current Output leakage current Active supply current ( AC,MOS level ) Active supply current ( AC,TTL level ) Stand by supply current ( AC,MOS level ) Conditions
( Vcc=5V10%, unless otherwise noted) Limits Min Typ Max Vcc+0.3V Units
VIH VIL VOH1 VOH2 VOL II IO Icc1 Icc2
2.2 -0.3 * 2.4
Vcc-0.5V
0.8 V 0.4 1 1
IOL=2mA VI =0 ~ Vcc S=VIH or OE=VIH, VI/O=0 ~ Vcc
S 0.2V Output-open Other inputs 0.2V or Vcc-0.2V Output-open S=VIL Other inputs=VIH or VIL S Vcc-0.2V Other inputs=0~Vcc f= 10MHz f= 1MHz f= 10MHz f= 1MHz -LW, -LI -L -HW, -HI -H
A
-
Icc3
50 25 60 30 1.0 1.0 -
80 30 90 40 200 100 60 30 3
mA
A
Icc4
Stand by supply current ( AC,TTL level )
S=V ,Other inputs= 0 ~ Vcc
mA
Note 1: Direction for current flowing into IC is indicated as positive (no mark) Note 2: Typical value is for Vcc=5.0V and Ta=25C
* -3.0V in case of AC (Pulse width 50ns)
CAPACITANCE
Symbol Parameter Input capacitance Output capacitance Conditions VI=GND, VI=25mVrms, f=1MHz VO=GND,VO=25mVrms, f=1MHz
(Vcc=5.0V10%, unless otherwise noted) Limits Typ Max Units
Min
CI CO
8 10 pF
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revision-K1.1e, ' 99.10.21
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS
Supply voltage Input pulse Input rise time and fall time Reference level 5.0V
(Vcc=5.0V10%, unless otherwise noted)
VIH=2.4V,VIL=0.6V (FP,TP,RT-70 ) VIH=3.0V,VIL=0V (FP,TP,RT-55 ) 5ns VOH=VOL=1.5V Transition is measured 500mV from steady state voltage.(for ten,tdis) Fig.1, CL=100pF (FP,TP,RT-70 ) CL=30pF (FP,TP,RT-55 ) CL=5pF (for ten,tdis)
1.8k DQ 990 CL
Output loads
CL Including scope and jig capacitance
Fig.1 Output load
(2) READ CYCLE
Limits Symbol Parameter Read cycle time Address access time Chip select access time Output enable access time Output disable time after S high Output disable time after OE high Output enable time after S low Output enable time after OE low Data valid time after address
M5M5408BFP,TP,RT-55 M5M5408BFP,TP,RT-70
Units
Min
Max
Min
Max
tCR ta(A) ta(S) ta(OE) tdis(S) tdis(OE) ten(S) ten(OE) tV(A)
55 55 55 25 20 20 10 5 10
70 70 70 35 25 25 10 5 10
ns ns ns ns ns ns ns ns ns
(3) WRITE CYCLE
Limits Symbol Parameter Write cycle time Write pulse width Address set up time Address set up time with respect to W high Chip select set up time Data set up time Data hold time Write recovery time Output disable time after W low Output disable time after OE high Output enable time after W high Output enable time after OE low
M5M5408BFP,TP,RT-55 M5M5408BFP,TP,RT-70
Units
Min
Max
Min
Max
tCW tw(W) tsu(A) tsu(A-WH) tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE)
55 40 0 50 50 25 0 0 20 20 5 5
70 50 0 60 60 30 0 0 25 25 5 5
ns ns ns ns ns ns ns ns ns ns ns ns
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revision-K1.1e, ' 99.10.21
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS Read cycle
A0~18 ta(A) ta(S) S
(Note3)
tCR
tv (A)
tdis (S) ta (OE)
(Note3)
OE
(Note3) W = "H" level
ten (OE) ten (S) tdis (OE)
(Note3)
DQ1~8
VALID DATA
Write cycle ( W control mode )
tCW A0~18 tsu (S) S
(Note3)
tsu (A-WH)
(Note3)
OE tsu (A) W tdis (W) tdis(OE) DQ1~8
DATA IN STABLE
tw (W)
trec (W)
ten(OE) ten (W)
tsu (D)
th (D)
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revision-K1.1e, ' 99.10.21
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle (S control mode)
tCW A0~18 tsu (A) S tsu (S) trec (W)
(Note5)
W
(Note3)
(Note4) (Note3)
tsu (D) DQ1~8
DATA IN STABLE
th (D)
Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during the overlap of a low S and a low W. Note 5: If W goes low simultaneously with or prior to S,the output remains in the high impedance state. Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode.
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revision-K1.1e, ' 99.10.21
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS
Symbol Parameter Test conditions Min Limits Typ. Max Units V V V
Vcc (PD) Power down supply voltage VI (S) Chip select input S Vcc(PD) 2.2V 2.2V Vcc(PD) 2.0V -LW, -LI Icc (PD) Power down supply current
Vcc=3.0V, SVcc-0.2V, Other inputs=0 ~ Vcc
2 2.2 -
Vcc(PD)
100 50 30 15
-L -HW, -HI -H
0.4 0.4
A A A A
Typical value is for Ta=25C
(2) TIMING REQUIREMINTS
Symbol Parameter Power down set up time Power down recovery time Limits Test conditions Min 0 5 Typ Max Units ns ms
tsu (PD) trec (PD)
(3) TIMING DIAGRAM
S control mode Vcc tsu (PD) 2.2V S SVcc - 0.2V 4.5V 4.5V trec (PD) 2.2V
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revision-K1.1e, ' 99.10.21
MITSUBISHI LSIs
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
Revision History Revision No. K0.1e K0.2e
History The first edition 1) Icc3 limit revised 2) Icc(PD) limit revised 3) Icc1,Icc2 conditions revised 1) Vcc Level in the Block Diagram revised 2) Icc3 limit (typ) revised The first product version Product Lineup Revised
Date '98.7.30 '99.6.3 '98.6.3 '98.6.3 '99.6.28 '99.6.28 '99.10.12 '99.10.21 Preliminary Preliminary Preliminary Preliminary Preliminary Preliminary -----
K0.3e K1.0e K1.1e
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